90 lines
2.8 KiB
C++
90 lines
2.8 KiB
C++
/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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main.cpp -- This is the top level file instantiating the modules and
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binding ports to signals.
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Original Author: Amit Rao, Synopsys, Inc.
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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#include "systemc.h"
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#include "stage1.h"
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#include "stage2.h"
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#include "stage3.h"
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#include "display.h"
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#include "numgen.h"
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int sc_main(int, char *[])
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{
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//Signals
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sc_signal<double> in1;
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sc_signal<double> in2;
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sc_signal<double> sum;
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sc_signal<double> diff;
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sc_signal<double> prod;
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sc_signal<double> quot;
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sc_signal<double> powr;
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//Clock
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sc_signal<bool> clk;
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numgen N("numgen"); //instance of `numgen' module
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N(in1, in2, clk ); //Positional port binding
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stage1 S1("stage1"); //instance of `stage1' module
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//Named port binding
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S1.in1(in1);
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S1.in2(in2);
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S1.sum(sum);
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S1.diff(diff);
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S1.clk(clk);
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stage2 S2("stage2"); //instance of `stage2' module
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S2(sum, diff, prod, quot, clk ); //Positional port binding
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stage3 S3("stage3"); //instance of `stage3' module
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S3( prod, quot, powr, clk); //Positional port binding
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display D("display"); //instance of `display' module
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D(powr, clk); //Positional port binding
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sc_start(0, SC_NS); //Initialize simulation
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for(int i = 0; i < 50; i++){
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clk.write(1);
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sc_start( 10, SC_NS );
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clk.write(0);
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sc_start( 10, SC_NS );
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}
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return 0;
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}
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