62 lines
2.7 KiB
Plaintext
62 lines
2.7 KiB
Plaintext
README for FIR
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===================================================================
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The example shows how to use the C++
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modeling with SystemC to model hardware properties. One important aspect of
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modeling with the Systemc classes is that you can use the same
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environment for different levels of abstraction, from very abstract down to
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RT-level.
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My example models a simple FIR filter which reads in samples with each
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input_valid signal and writing out the result when output_data_ready is
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high. The filter is a 16 tap FIR filter(fir.cc). The test bench feeds simply
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ascending values into the FIR(stimulus.cc) and the output is
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sampled (display.cc) and displayed with print statements.
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The basic structure looks like this:
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+--------------------------------------------------+
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| +-----------+ +-----------+ +-----------+ |
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| | | | | | | |
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| | stimuli |---->| FIR |-->| display | |
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| | | | | | | |
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| +-----------+ +-----------+ +-----------+ |
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| main |
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+--------------------------------------------------+
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In order to compile the example you have to execute 'make'. Please
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note that the file Makefile.defs contains the location of the SystemC
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class library, which might be different for you, depending on your
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installation. Once the compilation is finished, you will find an
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executable 'run.x'.
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Once I have evaluated the functionality for the FIR it might be
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interesting to "refine" the model further to get an better idea about
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the complexity of the design. When modeling with C++ using SystemC
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one can easily refine the FIR filter into a RTL style model.
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I have refined the FIR process under the assumption that I use 4
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cycles to do the whole computation. The structure looks now like
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this:
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+---------------------------------------------------+
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| +-----------+ +------------+ +-----------+ |
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| | | | FIR_top | | | |
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| | stimuli | | +--------+ | | display | |
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| | | | |FIR_FSM | | | | |
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| +-----------+ | +--------+ | +-----------+ |
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| | +--------+ | |
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| | |FIR_data| | |
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| | +--------+ | |
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| main +------------+ |
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+---------------------------------------------------+
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I have modeled a state machine(fir_fsm.cc) and a datapath(fir_data.cc)
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in order to distribute the operations into 4 cycles, which makes the
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model more difficult to read, but this models now a "RTL" like view to
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the architecture for this design.
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