data: publish complete Calculet NPU research archive
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// SPDX-License-Identifier: GPL-2.0
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/**
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* Copyright (c) 2024-2025 CALCULET Technologies Ltd. All rights reserved.
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*/
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#ifndef _CALCULET_UNIFIED_API_HPP_
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#define _CALCULET_UNIFIED_API_HPP_
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#include <cstdint>
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#include <cstddef>
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#include <string>
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#include <memory>
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#include <vector>
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extern "C" {
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#include <sys/types.h>
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#ifdef __linux__
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#include <linux/ioctl.h>
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#endif
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}
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// ============================================================================
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// Constants and Enums
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// ============================================================================
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#define CALCULET_READ_CHANNELS 8
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#define CALCULET_WRITE_CHANNELS 8
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#define CALCULET_TOTAL_CHANNELS (CALCULET_READ_CHANNELS + CALCULET_WRITE_CHANNELS)
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#define CALCULET_MAX_CHANNELS 32
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#define KS1_MAX_DEVICES 64
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#define KS1_MAX_PATH_LEN 512
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#define KS1_MAX_STRING_LEN 256
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#define KS1_MAX_UUID_LEN 64
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#define KS1_MAX_CHIPS 16
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#define MAX_PROCESS_ENTRIES 100
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#define CALCULET_GENERAL_IOCTL_MAGIC 'g'
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#define CALCULET_DMA_IOCTL_MAGIC 'd'
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#define CALCULET_SOC_IOCTL_MAGIC 's'
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#define CALCULET_NNC_IOCTL_MAGIC 'n'
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#define CALCULET_PCI_EP_IOCTL_MAGIC 'p'
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#define CALCULET_PROC_IOCTL_MAGIC 'r'
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#define _IOW_ _IOW
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#define _IOR_ _IOR
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#define _IOWR_ _IOWR
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#define _IO_ _IO
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namespace calrt {
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enum class InterfaceType : uint32_t {
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None = 0,
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PCIe = 1,
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USB,
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EMULATOR
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};
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enum class TransferDirection {
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DeviceToHost = 0, // C2H
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HostToDevice = 1, // H2C
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};
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enum class BarType {
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Bar2 = 2,
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Bar4 = 4
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};
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// ============================================================================
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// Data Structures
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// ============================================================================
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#pragma pack(push, 1)
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struct DeviceInfo {
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char product_name[KS1_MAX_STRING_LEN];
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char serial_number[KS1_MAX_STRING_LEN];
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char product_number[KS1_MAX_STRING_LEN];
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char calculet_uuid[KS1_MAX_UUID_LEN];
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uint16_t device_id;
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uint16_t vendor_id;
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uint16_t subsystem_device;
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uint16_t subsystem_vendor;
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struct {
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uint8_t domain;
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uint8_t bus;
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uint8_t device;
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uint8_t function;
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uint8_t link_speed;
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uint8_t link_width;
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} pci_info;
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struct {
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uint32_t major;
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uint32_t minor;
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char string[KS1_MAX_STRING_LEN];
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} driver_version;
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char firmware_version[12];
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uint64_t total_memory;
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double memory_bandwidth;
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uint32_t ddr_frequency;
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uint32_t max_power_limit;
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uint32_t temp_limit_ks1;
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};
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struct Bar64TransferParams {
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TransferDirection transfer_direction;
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BarType bar_type;
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uint64_t bar_offset;
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uint64_t bar_data;
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};
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struct Bar32TransferParams {
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TransferDirection transfer_direction;
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BarType bar_type;
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uint64_t bar_offset;
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uint32_t bar_data;
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};
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// DMA传输通道参数
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struct MemoryTransferParams {
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TransferDirection transfer_direction;
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int channel_id; // PCIe: 0-7, USB: ignored
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size_t size;
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uint8_t *host_address;
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uint64_t device_address;
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};
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struct MsiRequest {
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uint32_t msi_req; // 0-15
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};
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struct SerialNumberInfo {
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uint32_t chip_id;
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char sn[KS1_MAX_STRING_LEN];
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};
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struct ProcessInfo {
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int32_t pid;
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int32_t ppid;
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uint32_t uid;
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char comm[16];
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uint8_t is_active;
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uint8_t reserved[3];
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};
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struct ProcessList {
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int32_t count;
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int32_t board_index;
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ProcessInfo processes[MAX_PROCESS_ENTRIES];
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};
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struct CalrtDriverInfo_s {
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uint32_t max_version;
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uint32_t min_version;
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std::string path;
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InterfaceType interface_type;
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struct {
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uint8_t bus_number;
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uint8_t device_address;
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char serial_number[256];
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} usb_info;
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CalrtDriverInfo_s()
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: max_version(0)
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, min_version(0)
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, interface_type(InterfaceType::None) {
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usb_info.bus_number = 0;
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usb_info.device_address = 0;
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usb_info.serial_number[0] = '\0';
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}
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};
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#pragma pack(pop)
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inline const char* toString(InterfaceType type) {
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switch (type) {
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case InterfaceType::PCIe: return "PCIe";
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case InterfaceType::USB: return "USB";
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case InterfaceType::EMULATOR: return "EMULATOR";
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default: return "None";
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}
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}
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// IOCTL 定义
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enum calculet_general_ioctl_code {
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CALCULET_BOARD_INFO_CODE,
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CALCULET_BAR64_TRANSFER_CODE,
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CALCULET_BAR32_TRANSFER_CODE,
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CALCULET_GET_SN_CODE,
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CALCULET_GENERAL_IOCTL_MAX_NR,
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};
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enum calculet_dma_ioctl_code {
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CALCULET_BLOCK_DMA_TRANSFER_CODE,
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CALCULET_DMA_INTERRUPT_POLL_CODE,
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CALCULET_EP_MSI_REQ_CODE,
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CALCULET_SOFT_RESET_CODE,
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CALCULET_DMA_IOCTL_MAX_NR,
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};
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enum calculet_proc_ioctl_code {
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CALCULET_GET_PROCESS_LIST_CODE,
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CALCULET_PROC_IOCTL_MAX_NR,
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};
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#define CALCULET_BOARD_INFO _IOWR_(CALCULET_GENERAL_IOCTL_MAGIC, CALCULET_BOARD_INFO_CODE, DeviceInfo)
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#define CALCULET_BAR64_TRANSFER _IOWR_(CALCULET_GENERAL_IOCTL_MAGIC, CALCULET_BAR64_TRANSFER_CODE, Bar64TransferParams)
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#define CALCULET_BAR32_TRANSFER _IOWR_(CALCULET_GENERAL_IOCTL_MAGIC, CALCULET_BAR32_TRANSFER_CODE, Bar32TransferParams)
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#define CALCULET_GET_SN _IOWR_(CALCULET_GENERAL_IOCTL_MAGIC, CALCULET_GET_SN_CODE, SerialNumberInfo)
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#define CALCULET_BLOCK_DMA_TRANSFER _IOWR_(CALCULET_DMA_IOCTL_MAGIC, CALCULET_BLOCK_DMA_TRANSFER_CODE, MemoryTransferParams)
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#define CALCULET_INTERRUPT_POLL _IO_(CALCULET_DMA_IOCTL_MAGIC, CALCULET_DMA_INTERRUPT_POLL_CODE)
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#define CALCULET_EP_MSI_REQ _IOW_(CALCULET_PCI_EP_IOCTL_MAGIC, CALCULET_EP_MSI_REQ_CODE, MsiRequest)
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#define CALCULET_SOFT_RESET _IO_(CALCULET_PCI_EP_IOCTL_MAGIC, CALCULET_SOFT_RESET_CODE)
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#define CALCULET_GET_PROCESS_LIST _IOWR_(CALCULET_PROC_IOCTL_MAGIC, CALCULET_GET_PROCESS_LIST_CODE, ProcessList)
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}
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#endif /* _CALCULET_IOCTL_H_ */
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@@ -0,0 +1,64 @@
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#pragma once
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#include <cstdint>
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#define SYS_MAP_DEV_START_ADDR 0x0000000000 // 0 ~ 128MB
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#define SYS_MAP_DEV_END_ADDR 0x0007ffffff // 128MB
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#define SYS_MAP_SRAM_START_ADDR 0x0008000000 // 128MB ~ 146MB
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#define SYS_MAP_SRAM_END_ADDR 0x00091fffff // 18MB
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#define SYS_MAP_CCU_REG_START_ADDR 0x000a230000 //
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#define SYS_MAP_CCU_REG_SIZE 0x00004000 // 16KB
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#define SYS_MAP_DDR_START_ADDR 0x0100000000
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#define SYS_MAP_DDR_END_ADDR 0x3fffffffff
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#define CCU_MAP_DEV_START_ADDR SYS_MAP_DEV_START_ADDR
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#define CCU_MAP_DEV_END_ADDR SYS_MAP_DEV_END_ADDR
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#define CCU_MAP_SRAM_START_ADDR SYS_MAP_SRAM_START_ADDR
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#define CCU_MAP_SRAM_END_ADDR SYS_MAP_SRAM_END_ADDR
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#define CCU_MAP_CCU_REG_START_ADDR 0x000a000000
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#define CCU_MAP_CCU_REG_SIZE SYS_MAP_CCU_REG_SIZE
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#define CCU_MAP_VB_START_ADDR 0x000a100000
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#define CCU_MAP_VB_END_ADDR 0x000a1fffff
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#define CCU_MAP_DDR_START_ADDR 0x000a200000
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#define CCU_MAP_DDR_END_ADDR 0x0fffffffff
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#define CCU_DDR_BOUDARY 0x000a200000 // 162MB
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#define CCU_DDR_OFFSET 0x00f5e00000 // 4GB - 162MB
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#define CCU_DM0_OUTSTANDING 32
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#define MASK_UINT32 0xffffffff
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#define MASK_UINT64 0xffffffffffffffff
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// sys map
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// ============== sync mem map ==============
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#define MEM_ADDR_SYS_MAP_SYNC_UNIT_BASE 0x00a080000
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#define MEM_ADDR_SYNC_UNIT_SIZE (4 * 1024)
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// ============== cpu job queue ==============
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#define CSR_ADDR_SYS_MAP_JOB_QUEUE_BASE 0x00a23b000
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#define CSR_ADDR_JOB_QUEUE_SIZE (4*1024)
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// ==============ccu cfg==============
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#define CSR_ADDR_SYS_MAP_CCU0_BASE SYS_MAP_CCU_REG_START_ADDR
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#define CSR_ADDR_SYS_MAP_CCU1_BASE SYS_MAP_CCU_REG_START_ADDR + SYS_MAP_CCU_REG_SIZE
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#define CSR_ADDR_CCU_SIZE (16*1024)
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// ==============d2d cfg==============
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#define CSR_ADDR_SYS_MAP_D2D_BRIDGE_BASE 0x00a2e0000
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#define CSR_ADDR_D2D_BRIDGE_SIZE (4* 1024)
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// reg cmd registers
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#define CSR_ADDR_SYS_MAP_D2D_REG_CMD_BASE 0x00a2e0400
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#define CSR_ADDR_D2D_REG_CMD_SIZE (1*1024)
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// data cmd registers
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#define CSR_ADDR_SYS_MAP_D2D_DATA_CMD_BASE 0x00a2e0800
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#define CSR_ADDR_D2D_DATA_CMD_SIZE (1*1024)
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// ============== ddr and sram mem map ==============
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#define MEM_ADDR_CCU_MAP_SRAM_BASE ( 128UL*1024*1024) // 128 MB
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#define MEM_ADDR_CCU_MAP_DDR_BASE ( 162UL*1024*1024) // 162 MB
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#define MEM_ADDR_SYS_MAP_SRAM_BASE MEM_ADDR_CCU_MAP_SRAM_BASE
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#define MEM_ADDR_SYS_MAP_DDR_BASE ( 4L * 1024*1024*1024)
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#define MEM_ADDR_DDR_SIZE (256L * 1024*1024*1024) // 38 bit, 256GB
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#define MEM_ADDR_SRAM_SIZE ( 18*1024*1024) // 18 MB
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#define SYS_PMU_BASE_ADDR 0x0a238000
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@@ -0,0 +1,961 @@
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// Git: 572d614e85cb63375395c77d4e774a3be0fb7796
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// Generated at: 2025-01-06 11:42:54
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#pragma once
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#include <stdint.h>
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namespace ccu_csr {
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inline constexpr uint32_t csr_offset_reg_ccu_scl_program_addr = 0x0000;
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inline constexpr uint32_t csr_offset_reg_ccu_scl_start = 0x0004;
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inline constexpr uint32_t csr_offset_reg_ccu_scl_done = 0x0008;
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inline constexpr uint32_t csr_offset_reg_ccu_ddr_boundary = 0x000c;
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inline constexpr uint32_t csr_offset_reg_ccu_scl_ddr_offset = 0x0010;
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inline constexpr uint32_t csr_offset_reg_ccu_nscl_ddr_offset = 0x0014;
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inline constexpr uint32_t csr_offset_reg_ccu_pf_ctrl = 0x0018;
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inline constexpr uint32_t csr_offset_reg_ccu_stk_init_ctrl = 0x001c;
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inline constexpr uint32_t csr_offset_reg_ccu_scl_sram_ctrl = 0x0020;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_status0 = 0x1000;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_status1 = 0x1004;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_status2 = 0x1008;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_status3 = 0x100c;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_status4 = 0x1010;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_csr_fifo = 0x1014;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_csr_fifo_status = 0x1018;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_quant = 0x101c;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_axi_ctrl = 0x1020;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_function_en = 0x1024;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_instr_start_cmd = 0x1028;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_instr_end_cmd = 0x102c;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_instr_window_clk_cnt = 0x1030;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_load_start_cmd = 0x1034;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_load_end_cmd = 0x1038;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_load_window_clk_cnt = 0x103c;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_load_window_ar_valid_cnt = 0x1040;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_load_window_ar_hand_cnt = 0x1044;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_start_cmd = 0x1048;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_end_cmd = 0x104c;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_window_clk_cnt0 = 0x1050;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_window_clk_cnt1 = 0x1054;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_window_clk_cnt2 = 0x1058;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_window_clk_cnt3 = 0x105c;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_window_clk_cnt4 = 0x1060;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_window_clk_cnt5 = 0x1064;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_window_clk_cnt6 = 0x1068;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_window_clk_cnt7 = 0x106c;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_valid_cnt0 = 0x1070;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_valid_cnt1 = 0x1074;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_valid_cnt2 = 0x1078;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_valid_cnt3 = 0x107c;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_valid_cnt4 = 0x1080;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_valid_cnt5 = 0x1084;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_valid_cnt6 = 0x1088;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_valid_cnt7 = 0x108c;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_hand_cnt0 = 0x1090;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_hand_cnt1 = 0x1094;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_hand_cnt2 = 0x1098;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_hand_cnt3 = 0x109c;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_hand_cnt4 = 0x10a0;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_hand_cnt5 = 0x10a4;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_hand_cnt6 = 0x10a8;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_wr_hand_cnt7 = 0x10ac;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_ddr_start_cmd = 0x10b0;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_ddr_end_cmd = 0x10b4;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_ddr_window_clk_cnt = 0x10b8;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_ddr_axi0_ar_valid_cnt = 0x10bc;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_ddr_axi0_ar_hand_cnt = 0x10c0;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_ddr_axi0_r_valid_cnt = 0x10c4;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_ddr_axi0_r_hand_cnt = 0x10c8;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_ddr_axi1_ar_valid_cnt = 0x10cc;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_ddr_axi1_ar_hand_cnt = 0x10d0;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_ddr_axi1_r_valid_cnt = 0x10d4;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_ddr_axi1_r_hand_cnt = 0x10d8;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_ddr_axi2_ar_valid_cnt = 0x10dc;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_ddr_axi2_ar_hand_cnt = 0x10e0;
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inline constexpr uint32_t csr_offset_reg_ccu_dm0_ddr_axi2_r_valid_cnt = 0x10e4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm0_ddr_axi2_r_hand_cnt = 0x10e8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_model_config1_ping = 0x10ec;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_model_config1_pong = 0x10f0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_model_config2_ping = 0x10f4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_model_config2_pong = 0x10f8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_asmloop_base_addr_ping = 0x10fc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_asmloop_base_addr_pong = 0x1100;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_0_ping = 0x1104;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_0_pong = 0x1108;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_1_ping = 0x110c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_1_pong = 0x1110;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_2_ping = 0x1114;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_2_pong = 0x1118;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_3_ping = 0x111c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_3_pong = 0x1120;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_4_ping = 0x1124;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_4_pong = 0x1128;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_5_ping = 0x112c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_5_pong = 0x1130;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_6_ping = 0x1134;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_6_pong = 0x1138;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_7_ping = 0x113c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_7_pong = 0x1140;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_8_ping = 0x1144;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_8_pong = 0x1148;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_9_ping = 0x114c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_9_pong = 0x1150;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_10_ping = 0x1154;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_10_pong = 0x1158;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_11_ping = 0x115c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_11_pong = 0x1160;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_12_ping = 0x1164;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_12_pong = 0x1168;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_13_ping = 0x116c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_13_pong = 0x1170;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_14_ping = 0x1174;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_14_pong = 0x1178;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_15_ping = 0x117c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_15_pong = 0x1180;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_16_ping = 0x1184;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_16_pong = 0x1188;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_17_ping = 0x118c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_17_pong = 0x1190;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_18_ping = 0x1194;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_18_pong = 0x1198;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_19_ping = 0x119c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_19_pong = 0x11a0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_20_ping = 0x11a4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_20_pong = 0x11a8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_21_ping = 0x11ac;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_21_pong = 0x11b0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_22_ping = 0x11b4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_22_pong = 0x11b8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_23_ping = 0x11bc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_23_pong = 0x11c0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_24_ping = 0x11c4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_24_pong = 0x11c8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_25_ping = 0x11cc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_25_pong = 0x11d0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_26_ping = 0x11d4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_26_pong = 0x11d8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_27_ping = 0x11dc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_27_pong = 0x11e0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_28_ping = 0x11e4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_28_pong = 0x11e8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_29_ping = 0x11ec;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_29_pong = 0x11f0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_30_ping = 0x11f4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_30_pong = 0x11f8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_31_ping = 0x11fc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_31_pong = 0x1200;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_32_ping = 0x1204;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_32_pong = 0x1208;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_33_ping = 0x120c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_33_pong = 0x1210;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_34_ping = 0x1214;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_34_pong = 0x1218;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_35_ping = 0x121c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_35_pong = 0x1220;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_36_ping = 0x1224;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_36_pong = 0x1228;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_37_ping = 0x122c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_37_pong = 0x1230;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_38_ping = 0x1234;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_38_pong = 0x1238;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_39_ping = 0x123c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_39_pong = 0x1240;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_40_ping = 0x1244;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_40_pong = 0x1248;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_41_ping = 0x124c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_41_pong = 0x1250;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_42_ping = 0x1254;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_42_pong = 0x1258;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_43_ping = 0x125c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_43_pong = 0x1260;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_44_ping = 0x1264;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_44_pong = 0x1268;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_45_ping = 0x126c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_45_pong = 0x1270;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_46_ping = 0x1274;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_46_pong = 0x1278;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_47_ping = 0x127c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_47_pong = 0x1280;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_48_ping = 0x1284;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_48_pong = 0x1288;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_49_ping = 0x128c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_49_pong = 0x1290;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_50_ping = 0x1294;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_50_pong = 0x1298;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_51_ping = 0x129c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_51_pong = 0x12a0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_52_ping = 0x12a4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_52_pong = 0x12a8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_53_ping = 0x12ac;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_53_pong = 0x12b0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_54_ping = 0x12b4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_54_pong = 0x12b8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_55_ping = 0x12bc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_55_pong = 0x12c0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_56_ping = 0x12c4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_56_pong = 0x12c8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_57_ping = 0x12cc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_57_pong = 0x12d0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_58_ping = 0x12d4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_58_pong = 0x12d8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_59_ping = 0x12dc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_59_pong = 0x12e0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_60_ping = 0x12e4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_modelcfg_reserved_60_pong = 0x12e8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_cfg_ready_0_ping = 0x12ec;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_cfg_ready_1_ping = 0x12f0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_cfg_ready_0_pong = 0x12f4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_cfg_ready_1_pong = 0x12f8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_status0 = 0x1400;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_status1 = 0x1404;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_status2 = 0x1408;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_status3 = 0x140c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_status4 = 0x1410;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_csr_fifo = 0x1414;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_csr_fifo_status = 0x1418;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_function_en = 0x141c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_instr_start_cmd = 0x1420;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_instr_end_cmd = 0x1424;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_instr_window_clk_cnt = 0x1428;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_start_cmd = 0x142c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_end_cmd = 0x1430;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_clk_cnt = 0x1434;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_valid_cnt0 = 0x1438;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_valid_cnt1 = 0x143c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_valid_cnt2 = 0x1440;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_valid_cnt3 = 0x1444;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_valid_cnt4 = 0x1448;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_valid_cnt5 = 0x144c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_valid_cnt6 = 0x1450;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_valid_cnt7 = 0x1454;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_valid_cnt8 = 0x1458;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_valid_cnt9 = 0x145c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_valid_cnt10 = 0x1460;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_valid_cnt11 = 0x1464;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_valid_cnt12 = 0x1468;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_valid_cnt13 = 0x146c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_valid_cnt14 = 0x1470;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_valid_cnt15 = 0x1474;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_hand_cnt0 = 0x1478;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_hand_cnt1 = 0x147c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_hand_cnt2 = 0x1480;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_hand_cnt3 = 0x1484;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_hand_cnt4 = 0x1488;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_hand_cnt5 = 0x148c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_hand_cnt6 = 0x1490;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_hand_cnt7 = 0x1494;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_hand_cnt8 = 0x1498;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_hand_cnt9 = 0x149c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_hand_cnt10 = 0x14a0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_hand_cnt11 = 0x14a4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_hand_cnt12 = 0x14a8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_hand_cnt13 = 0x14ac;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_hand_cnt14 = 0x14b0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_load_window_ar_hand_cnt15 = 0x14b4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_start_cmd = 0x14b8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_end_cmd = 0x14bc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_window_clk_cnt0 = 0x14c0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_window_clk_cnt1 = 0x14c4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_window_clk_cnt2 = 0x14c8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_window_clk_cnt3 = 0x14cc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_window_clk_cnt4 = 0x14d0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_window_clk_cnt5 = 0x14d4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_window_clk_cnt6 = 0x14d8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_window_clk_cnt7 = 0x14dc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_window_clk_cnt8 = 0x14e0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_window_clk_cnt9 = 0x14e4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_window_clk_cnt10 = 0x14e8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_window_clk_cnt11 = 0x14ec;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_window_clk_cnt12 = 0x14f0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_window_clk_cnt13 = 0x14f4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_window_clk_cnt14 = 0x14f8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_window_clk_cnt15 = 0x14fc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_valid_cnt0 = 0x1500;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_valid_cnt1 = 0x1504;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_valid_cnt2 = 0x1508;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_valid_cnt3 = 0x150c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_valid_cnt4 = 0x1510;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_valid_cnt5 = 0x1514;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_valid_cnt6 = 0x1518;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_valid_cnt7 = 0x151c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_valid_cnt8 = 0x1520;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_valid_cnt9 = 0x1524;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_valid_cnt10 = 0x1528;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_valid_cnt11 = 0x152c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_valid_cnt12 = 0x1530;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_valid_cnt13 = 0x1534;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_valid_cnt14 = 0x1538;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_valid_cnt15 = 0x153c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_hand_cnt0 = 0x1540;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_hand_cnt1 = 0x1544;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_hand_cnt2 = 0x1548;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_hand_cnt3 = 0x154c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_hand_cnt4 = 0x1550;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_hand_cnt5 = 0x1554;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_hand_cnt6 = 0x1558;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_hand_cnt7 = 0x155c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_hand_cnt8 = 0x1560;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_hand_cnt9 = 0x1564;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_hand_cnt10 = 0x1568;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_hand_cnt11 = 0x156c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_hand_cnt12 = 0x1570;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_hand_cnt13 = 0x1574;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_hand_cnt14 = 0x1578;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib0_hand_cnt15 = 0x157c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_valid_cnt0 = 0x1580;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_valid_cnt1 = 0x1584;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_valid_cnt2 = 0x1588;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_valid_cnt3 = 0x158c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_valid_cnt4 = 0x1590;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_valid_cnt5 = 0x1594;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_valid_cnt6 = 0x1598;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_valid_cnt7 = 0x159c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_valid_cnt8 = 0x15a0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_valid_cnt9 = 0x15a4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_valid_cnt10 = 0x15a8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_valid_cnt11 = 0x15ac;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_valid_cnt12 = 0x15b0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_valid_cnt13 = 0x15b4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_valid_cnt14 = 0x15b8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_valid_cnt15 = 0x15bc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_hand_cnt0 = 0x15c0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_hand_cnt1 = 0x15c4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_hand_cnt2 = 0x15c8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_hand_cnt3 = 0x15cc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_hand_cnt4 = 0x15d0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_hand_cnt5 = 0x15d4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_hand_cnt6 = 0x15d8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_hand_cnt7 = 0x15dc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_hand_cnt8 = 0x15e0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_hand_cnt9 = 0x15e4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_hand_cnt10 = 0x15e8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_hand_cnt11 = 0x15ec;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_hand_cnt12 = 0x15f0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_hand_cnt13 = 0x15f4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_hand_cnt14 = 0x15f8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib1_hand_cnt15 = 0x15fc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_valid_cnt0 = 0x1600;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_valid_cnt1 = 0x1604;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_valid_cnt2 = 0x1608;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_valid_cnt3 = 0x160c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_valid_cnt4 = 0x1610;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_valid_cnt5 = 0x1614;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_valid_cnt6 = 0x1618;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_valid_cnt7 = 0x161c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_valid_cnt8 = 0x1620;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_valid_cnt9 = 0x1624;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_valid_cnt10 = 0x1628;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_valid_cnt11 = 0x162c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_valid_cnt12 = 0x1630;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_valid_cnt13 = 0x1634;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_valid_cnt14 = 0x1638;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_valid_cnt15 = 0x163c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_hand_cnt0 = 0x1640;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_hand_cnt1 = 0x1644;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_hand_cnt2 = 0x1648;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_hand_cnt3 = 0x164c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_hand_cnt4 = 0x1650;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_hand_cnt5 = 0x1654;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_hand_cnt6 = 0x1658;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_hand_cnt7 = 0x165c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_hand_cnt8 = 0x1660;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_hand_cnt9 = 0x1664;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_hand_cnt10 = 0x1668;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_hand_cnt11 = 0x166c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_hand_cnt12 = 0x1670;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_hand_cnt13 = 0x1674;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_hand_cnt14 = 0x1678;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_wr_gib2_hand_cnt15 = 0x167c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_status0 = 0x1800;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_status1 = 0x1804;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_status2 = 0x1808;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_status3 = 0x180c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_status4 = 0x1810;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_status5 = 0x1814;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_csr_fifo = 0x1818;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_csr_fifo_status = 0x181c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_quant = 0x1820;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_axi_ctrl = 0x1824;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_function_en = 0x1828;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_instr_start_cmd = 0x182c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_instr_end_cmd = 0x1830;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_instr_window_clk_cnt = 0x1834;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_start_cmd = 0x1838;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_end_cmd = 0x183c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_clk_cnt = 0x1840;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_valid_cnt0 = 0x1844;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_valid_cnt1 = 0x1848;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_valid_cnt2 = 0x184c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_valid_cnt3 = 0x1850;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_valid_cnt4 = 0x1854;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_valid_cnt5 = 0x1858;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_valid_cnt6 = 0x185c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_valid_cnt7 = 0x1860;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_valid_cnt8 = 0x1864;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_valid_cnt9 = 0x1868;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_valid_cnt10 = 0x186c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_valid_cnt11 = 0x1870;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_valid_cnt12 = 0x1874;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_valid_cnt13 = 0x1878;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_valid_cnt14 = 0x187c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_valid_cnt15 = 0x1880;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_hand_cnt0 = 0x1884;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_hand_cnt1 = 0x1888;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_hand_cnt2 = 0x188c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_hand_cnt3 = 0x1890;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_hand_cnt4 = 0x1894;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_hand_cnt5 = 0x1898;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_hand_cnt6 = 0x189c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_hand_cnt7 = 0x18a0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_hand_cnt8 = 0x18a4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_hand_cnt9 = 0x18a8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_hand_cnt10 = 0x18ac;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_hand_cnt11 = 0x18b0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_hand_cnt12 = 0x18b4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_hand_cnt13 = 0x18b8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_hand_cnt14 = 0x18bc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_load_window_ar_hand_cnt15 = 0x18c0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_start_cmd = 0x18c4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_end_cmd = 0x18c8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_window_clk_cnt0 = 0x18cc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_window_clk_cnt1 = 0x18d0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_window_clk_cnt2 = 0x18d4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_window_clk_cnt3 = 0x18d8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_window_clk_cnt4 = 0x18dc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_window_clk_cnt5 = 0x18e0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_window_clk_cnt6 = 0x18e4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_window_clk_cnt7 = 0x18e8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_window_clk_cnt8 = 0x18ec;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_window_clk_cnt9 = 0x18f0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_window_clk_cnt10 = 0x18f4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_window_clk_cnt11 = 0x18f8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_window_clk_cnt12 = 0x18fc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_window_clk_cnt13 = 0x1900;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_window_clk_cnt14 = 0x1904;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_window_clk_cnt15 = 0x1908;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_valid_cnt0 = 0x190c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_valid_cnt1 = 0x1910;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_valid_cnt2 = 0x1914;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_valid_cnt3 = 0x1918;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_valid_cnt4 = 0x191c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_valid_cnt5 = 0x1920;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_valid_cnt6 = 0x1924;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_valid_cnt7 = 0x1928;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_valid_cnt8 = 0x192c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_valid_cnt9 = 0x1930;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_valid_cnt10 = 0x1934;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_valid_cnt11 = 0x1938;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_valid_cnt12 = 0x193c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_valid_cnt13 = 0x1940;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_valid_cnt14 = 0x1944;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_valid_cnt15 = 0x1948;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_hand_cnt0 = 0x194c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_hand_cnt1 = 0x1950;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_hand_cnt2 = 0x1954;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_hand_cnt3 = 0x1958;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_hand_cnt4 = 0x195c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_hand_cnt5 = 0x1960;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_hand_cnt6 = 0x1964;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_hand_cnt7 = 0x1968;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_hand_cnt8 = 0x196c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_hand_cnt9 = 0x1970;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_hand_cnt10 = 0x1974;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_hand_cnt11 = 0x1978;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_hand_cnt12 = 0x197c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_hand_cnt13 = 0x1980;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_hand_cnt14 = 0x1984;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst0_hand_cnt15 = 0x1988;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_valid_cnt0 = 0x198c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_valid_cnt1 = 0x1990;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_valid_cnt2 = 0x1994;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_valid_cnt3 = 0x1998;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_valid_cnt4 = 0x199c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_valid_cnt5 = 0x19a0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_valid_cnt6 = 0x19a4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_valid_cnt7 = 0x19a8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_valid_cnt8 = 0x19ac;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_valid_cnt9 = 0x19b0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_valid_cnt10 = 0x19b4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_valid_cnt11 = 0x19b8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_valid_cnt12 = 0x19bc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_valid_cnt13 = 0x19c0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_valid_cnt14 = 0x19c4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_valid_cnt15 = 0x19c8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_hand_cnt0 = 0x19cc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_hand_cnt1 = 0x19d0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_hand_cnt2 = 0x19d4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_hand_cnt3 = 0x19d8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_hand_cnt4 = 0x19dc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_hand_cnt5 = 0x19e0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_hand_cnt6 = 0x19e4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_hand_cnt7 = 0x19e8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_hand_cnt8 = 0x19ec;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_hand_cnt9 = 0x19f0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_hand_cnt10 = 0x19f4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_hand_cnt11 = 0x19f8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_hand_cnt12 = 0x19fc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_hand_cnt13 = 0x1a00;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_hand_cnt14 = 0x1a04;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_wr_dst1_hand_cnt15 = 0x1a08;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_ddr_start_cmd = 0x1a0c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_ddr_end_cmd = 0x1a10;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_ddr_window_clk_cnt = 0x1a14;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_ddr_axi0_aw_valid_cnt = 0x1a18;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_ddr_axi0_aw_hand_cnt = 0x1a1c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_ddr_axi0_w_valid_cnt = 0x1a20;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_ddr_axi0_w_hand_cnt = 0x1a24;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_ddr_axi1_aw_valid_cnt = 0x1a28;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_ddr_axi1_aw_hand_cnt = 0x1a2c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_ddr_axi1_w_valid_cnt = 0x1a30;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_ddr_axi1_w_hand_cnt = 0x1a34;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_ddr_axi2_aw_valid_cnt = 0x1a38;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_ddr_axi2_aw_hand_cnt = 0x1a3c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_ddr_axi2_w_valid_cnt = 0x1a40;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_ddr_axi2_w_hand_cnt = 0x1a44;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_status0 = 0x1c00;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_status1 = 0x1c04;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_status2 = 0x1c08;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_status3 = 0x1c0c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_status4 = 0x1c10;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_status5 = 0x1c14;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_status6 = 0x1c18;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_csr_fifo = 0x1c1c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_csr_fifo_status = 0x1c20;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_function_en = 0x1c24;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_instr_start_cmd = 0x1c28;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_instr_end_cmd = 0x1c2c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_instr_window_clk_cnt = 0x1c30;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_start_cmd = 0x1c34;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_end_cmd = 0x1c38;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_clk_cnt = 0x1c3c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_valid_cnt0 = 0x1c40;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_valid_cnt1 = 0x1c44;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_valid_cnt2 = 0x1c48;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_valid_cnt3 = 0x1c4c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_valid_cnt4 = 0x1c50;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_valid_cnt5 = 0x1c54;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_valid_cnt6 = 0x1c58;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_valid_cnt7 = 0x1c5c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_valid_cnt8 = 0x1c60;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_valid_cnt9 = 0x1c64;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_valid_cnt10 = 0x1c68;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_valid_cnt11 = 0x1c6c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_valid_cnt12 = 0x1c70;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_valid_cnt13 = 0x1c74;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_valid_cnt14 = 0x1c78;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_valid_cnt15 = 0x1c7c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_hand_cnt0 = 0x1c80;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_hand_cnt1 = 0x1c84;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_hand_cnt2 = 0x1c88;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_hand_cnt3 = 0x1c8c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_hand_cnt4 = 0x1c90;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_hand_cnt5 = 0x1c94;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_hand_cnt6 = 0x1c98;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_hand_cnt7 = 0x1c9c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_hand_cnt8 = 0x1ca0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_hand_cnt9 = 0x1ca4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_hand_cnt10 = 0x1ca8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_hand_cnt11 = 0x1cac;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_hand_cnt12 = 0x1cb0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_hand_cnt13 = 0x1cb4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_hand_cnt14 = 0x1cb8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_load_window_ar_hand_cnt15 = 0x1cbc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_start_cmd = 0x1cc0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_end_cmd = 0x1cc4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_window_clk_cnt0 = 0x1cc8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_window_clk_cnt1 = 0x1ccc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_window_clk_cnt2 = 0x1cd0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_window_clk_cnt3 = 0x1cd4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_window_clk_cnt4 = 0x1cd8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_window_clk_cnt5 = 0x1cdc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_window_clk_cnt6 = 0x1ce0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_window_clk_cnt7 = 0x1ce4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_window_clk_cnt8 = 0x1ce8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_window_clk_cnt9 = 0x1cec;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_window_clk_cnt10 = 0x1cf0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_window_clk_cnt11 = 0x1cf4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_window_clk_cnt12 = 0x1cf8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_window_clk_cnt13 = 0x1cfc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_window_clk_cnt14 = 0x1d00;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_window_clk_cnt15 = 0x1d04;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_valid_cnt0 = 0x1d08;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_valid_cnt1 = 0x1d0c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_valid_cnt2 = 0x1d10;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_valid_cnt3 = 0x1d14;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_valid_cnt4 = 0x1d18;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_valid_cnt5 = 0x1d1c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_valid_cnt6 = 0x1d20;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_valid_cnt7 = 0x1d24;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_valid_cnt8 = 0x1d28;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_valid_cnt9 = 0x1d2c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_valid_cnt10 = 0x1d30;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_valid_cnt11 = 0x1d34;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_valid_cnt12 = 0x1d38;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_valid_cnt13 = 0x1d3c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_valid_cnt14 = 0x1d40;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_valid_cnt15 = 0x1d44;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_hand_cnt0 = 0x1d48;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_hand_cnt1 = 0x1d4c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_hand_cnt2 = 0x1d50;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_hand_cnt3 = 0x1d54;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_hand_cnt4 = 0x1d58;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_hand_cnt5 = 0x1d5c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_hand_cnt6 = 0x1d60;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_hand_cnt7 = 0x1d64;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_hand_cnt8 = 0x1d68;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_hand_cnt9 = 0x1d6c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_hand_cnt10 = 0x1d70;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_hand_cnt11 = 0x1d74;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_hand_cnt12 = 0x1d78;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_hand_cnt13 = 0x1d7c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_hand_cnt14 = 0x1d80;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_wr_dst0_hand_cnt15 = 0x1d84;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_csr_fifo = 0x2000;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_csr_fifo_status = 0x2004;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_quant = 0x2008;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_wr_mask = 0x200c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_mask0 = 0x2010;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_mask1 = 0x2014;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_mask2 = 0x2018;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_mask3 = 0x201c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_mask4 = 0x2020;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_mask5 = 0x2024;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_mask6 = 0x2028;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_mask7 = 0x202c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_mask8 = 0x2030;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_mask9 = 0x2034;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_mask10 = 0x2038;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_mask11 = 0x203c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_mask12 = 0x2040;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_mask13 = 0x2044;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_mask14 = 0x2048;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_mask15 = 0x204c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vu_core_ctrl = 0x2050;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_core_ctrl = 0x2400;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_csr_fifo = 0x2404;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_csr_fifo_status = 0x2408;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_quant = 0x240c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_perf_cfg = 0x2410;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_ctrl = 0x2414;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_wndw_start_ctrl = 0x2418;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_wndw_end_ctrl = 0x241c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_wndw_port_0 = 0x2420;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_wndw_port_1 = 0x2424;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_wndw_port_2 = 0x2428;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_wndw_port_3 = 0x242c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_wndw_port_4 = 0x2430;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_wndw_port_5 = 0x2434;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_wndw_port_6 = 0x2438;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_wndw_port_7 = 0x243c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_vld_port_0 = 0x2440;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_vld_port_1 = 0x2444;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_vld_port_2 = 0x2448;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_vld_port_3 = 0x244c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_vld_port_4 = 0x2450;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_vld_port_5 = 0x2454;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_vld_port_6 = 0x2458;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_vld_port_7 = 0x245c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_transmited_port_0 = 0x2460;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_transmited_port_1 = 0x2464;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_transmited_port_2 = 0x2468;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_transmited_port_3 = 0x246c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_transmited_port_4 = 0x2470;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_transmited_port_5 = 0x2474;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_transmited_port_6 = 0x2478;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_tu_hpmc_wrt_vb_transmited_port_7 = 0x247c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_instr_counter_ctrl = 0x2800;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_instr_hpmc_counter_ctrl = 0x2804;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm0_instr_sent_cnt_l = 0x2808;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_instr_sent_cnt_l = 0x280c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_instr_sent_cnt_l = 0x2810;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_instr_sent_cnt_l = 0x2814;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_gemm_instr_sent_cnt_l = 0x2818;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vec_instr_sent_cnt_l = 0x281c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm0_instr_sent_cnt_h = 0x2820;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_instr_sent_cnt_h = 0x2824;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_instr_sent_cnt_h = 0x2828;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_instr_sent_cnt_h = 0x282c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_gemm_instr_sent_cnt_h = 0x2830;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vec_instr_sent_cnt_h = 0x2834;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm0_instr_done_cnt_l = 0x2838;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_instr_done_cnt_l = 0x283c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_instr_done_cnt_l = 0x2840;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_instr_done_cnt_l = 0x2844;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_gemm_instr_done_cnt_l = 0x2848;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vec_instr_done_cnt_l = 0x284c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm0_instr_done_cnt_h = 0x2850;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_instr_done_cnt_h = 0x2854;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_instr_done_cnt_h = 0x2858;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_instr_done_cnt_h = 0x285c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_gemm_instr_done_cnt_h = 0x2860;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vec_instr_done_cnt_h = 0x2864;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_counter_status = 0x2868;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm0_instr_hpmc_cnt_l = 0x286c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_instr_hpmc_cnt_l = 0x2870;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_instr_hpmc_cnt_l = 0x2874;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_instr_hpmc_cnt_l = 0x2878;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_gemm_instr_hpmc_cnt_l = 0x287c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vec_instr_hpmc_cnt_l = 0x2880;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm0_instr_hpmc_cnt_h = 0x2884;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_instr_hpmc_cnt_h = 0x2888;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_instr_hpmc_cnt_h = 0x288c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_instr_hpmc_cnt_h = 0x2890;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_gemm_instr_hpmc_cnt_h = 0x2894;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vec_instr_hpmc_cnt_h = 0x2898;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm0_hpmc_start_ctrl_l = 0x289c;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm0_hpmc_start_ctrl_h = 0x28a0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm0_hpmc_end_ctrl_l = 0x28a4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm0_hpmc_end_ctrl_h = 0x28a8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_hpmc_start_ctrl_l = 0x28ac;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_hpmc_start_ctrl_h = 0x28b0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_hpmc_end_ctrl_l = 0x28b4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm1_hpmc_end_ctrl_h = 0x28b8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_hpmc_start_ctrl_l = 0x28bc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_hpmc_start_ctrl_h = 0x28c0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_hpmc_end_ctrl_l = 0x28c4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm2_hpmc_end_ctrl_h = 0x28c8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_hpmc_start_ctrl_l = 0x28cc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_hpmc_start_ctrl_h = 0x28d0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_hpmc_end_ctrl_l = 0x28d4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_dm3_hpmc_end_ctrl_h = 0x28d8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_gemm_hpmc_start_ctrl_l = 0x28dc;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_gemm_hpmc_start_ctrl_h = 0x28e0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_gemm_hpmc_end_ctrl_l = 0x28e4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_gemm_hpmc_end_ctrl_h = 0x28e8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vec_hpmc_start_ctrl_l = 0x28ec;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vec_hpmc_start_ctrl_h = 0x28f0;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vec_hpmc_end_ctrl_l = 0x28f4;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_vec_hpmc_end_ctrl_h = 0x28f8;
|
||||
inline constexpr uint32_t csr_offset_reg_ccu_clock_en_ctrl = 0x28fc;
|
||||
inline constexpr uint32_t csr_offset_reg_sch_ctrl = 0x2900;
|
||||
} // namespace ccu_csr
|
||||
|
||||
namespace jobq_csr {
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_init = 0x0000;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_status = 0x0004;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_push_ptr = 0x0008;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_pop_ptr = 0x000c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_usage = 0x0010;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_push_lo = 0x0020;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_push_hi = 0x0030;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_pop_lo = 0x0040;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_pop_hi = 0x0050;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_init = 0x0060;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_status = 0x0064;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_push_ptr = 0x0068;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_pop_ptr = 0x006c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_usage = 0x0070;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_push_lo = 0x0080;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_push_hi = 0x0090;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_pop_lo = 0x00a0;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_pop_hi = 0x00b0;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry0_lo = 0x0100;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry0_hi = 0x0104;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry1_lo = 0x0108;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry1_hi = 0x010c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry2_lo = 0x0110;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry2_hi = 0x0114;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry3_lo = 0x0118;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry3_hi = 0x011c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry4_lo = 0x0120;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry4_hi = 0x0124;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry5_lo = 0x0128;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry5_hi = 0x012c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry6_lo = 0x0130;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry6_hi = 0x0134;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry7_lo = 0x0138;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry7_hi = 0x013c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry8_lo = 0x0140;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry8_hi = 0x0144;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry9_lo = 0x0148;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry9_hi = 0x014c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry10_lo = 0x0150;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry10_hi = 0x0154;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry11_lo = 0x0158;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry11_hi = 0x015c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry12_lo = 0x0160;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry12_hi = 0x0164;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry13_lo = 0x0168;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry13_hi = 0x016c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry14_lo = 0x0170;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry14_hi = 0x0174;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry15_lo = 0x0178;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry15_hi = 0x017c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry16_lo = 0x0180;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry16_hi = 0x0184;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry17_lo = 0x0188;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry17_hi = 0x018c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry18_lo = 0x0190;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry18_hi = 0x0194;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry19_lo = 0x0198;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry19_hi = 0x019c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry20_lo = 0x01a0;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry20_hi = 0x01a4;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry21_lo = 0x01a8;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry21_hi = 0x01ac;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry22_lo = 0x01b0;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry22_hi = 0x01b4;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry23_lo = 0x01b8;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry23_hi = 0x01bc;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry24_lo = 0x01c0;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry24_hi = 0x01c4;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry25_lo = 0x01c8;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry25_hi = 0x01cc;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry26_lo = 0x01d0;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry26_hi = 0x01d4;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry27_lo = 0x01d8;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry27_hi = 0x01dc;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry28_lo = 0x01e0;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry28_hi = 0x01e4;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry29_lo = 0x01e8;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry29_hi = 0x01ec;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry30_lo = 0x01f0;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry30_hi = 0x01f4;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry31_lo = 0x01f8;
|
||||
inline constexpr uint32_t csr_offset_reg_job_start_q_entry31_hi = 0x01fc;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry0_lo = 0x0200;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry0_hi = 0x0204;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry1_lo = 0x0208;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry1_hi = 0x020c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry2_lo = 0x0210;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry2_hi = 0x0214;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry3_lo = 0x0218;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry3_hi = 0x021c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry4_lo = 0x0220;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry4_hi = 0x0224;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry5_lo = 0x0228;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry5_hi = 0x022c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry6_lo = 0x0230;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry6_hi = 0x0234;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry7_lo = 0x0238;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry7_hi = 0x023c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry8_lo = 0x0240;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry8_hi = 0x0244;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry9_lo = 0x0248;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry9_hi = 0x024c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry10_lo = 0x0250;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry10_hi = 0x0254;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry11_lo = 0x0258;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry11_hi = 0x025c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry12_lo = 0x0260;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry12_hi = 0x0264;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry13_lo = 0x0268;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry13_hi = 0x026c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry14_lo = 0x0270;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry14_hi = 0x0274;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry15_lo = 0x0278;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry15_hi = 0x027c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry16_lo = 0x0280;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry16_hi = 0x0284;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry17_lo = 0x0288;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry17_hi = 0x028c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry18_lo = 0x0290;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry18_hi = 0x0294;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry19_lo = 0x0298;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry19_hi = 0x029c;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry20_lo = 0x02a0;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry20_hi = 0x02a4;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry21_lo = 0x02a8;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry21_hi = 0x02ac;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry22_lo = 0x02b0;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry22_hi = 0x02b4;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry23_lo = 0x02b8;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry23_hi = 0x02bc;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry24_lo = 0x02c0;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry24_hi = 0x02c4;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry25_lo = 0x02c8;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry25_hi = 0x02cc;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry26_lo = 0x02d0;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry26_hi = 0x02d4;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry27_lo = 0x02d8;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry27_hi = 0x02dc;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry28_lo = 0x02e0;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry28_hi = 0x02e4;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry29_lo = 0x02e8;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry29_hi = 0x02ec;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry30_lo = 0x02f0;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry30_hi = 0x02f4;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry31_lo = 0x02f8;
|
||||
inline constexpr uint32_t csr_offset_reg_job_end_q_entry31_hi = 0x02fc;
|
||||
} // namespace jobq_csr
|
||||
|
||||
namespace d2d_bridge_csr {
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_id_cfg = 0x0000;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_num_cfg = 0x0004;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_ring_cfg = 0x0008;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_loopback_cfg = 0x000c;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_west_d2d_ip_cfg = 0x0010;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_east_d2d_ip_cfg = 0x0014;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_sram_cfg = 0x0018;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_data_inject_mode_cfg = 0x001c;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_data_inject_trig_cfg = 0x0020;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_cmd_data_timeout_cfg = 0x0024;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_data_direction_cfg = 0x0028;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_perf_cnt_cfg = 0x002c;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_mem_rd_perf_cnt_val = 0x0030;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_mem_rd_perf_timer_val_low = 0x0034;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_mem_rd_perf_timer_val_high = 0x0038;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_mem_wr_perf_cnt_val = 0x003c;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_mem_wr_perf_timer_val_low = 0x0040;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_mem_wr_perf_timer_val_high = 0x0044;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_ring_perf_cnt_val = 0x0048;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_ring_perf_timer_val_low = 0x004c;
|
||||
inline constexpr uint32_t csr_offset_reg_bridge_ring_perf_timer_val_high = 0x0050;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_addr_cfg_0 = 0x0400;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_addr_cfg_1 = 0x0404;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_addr_cfg_2 = 0x0408;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_addr_cfg_3 = 0x040c;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_addr_cfg_4 = 0x0410;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_addr_cfg_5 = 0x0414;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_addr_cfg_6 = 0x0418;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_addr_cfg_7 = 0x041c;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_value_cfg_0 = 0x0420;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_value_cfg_1 = 0x0424;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_value_cfg_2 = 0x0428;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_value_cfg_3 = 0x042c;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_value_cfg_4 = 0x0430;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_value_cfg_5 = 0x0434;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_value_cfg_6 = 0x0438;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_value_cfg_7 = 0x043c;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_cmd_cfg_0 = 0x0440;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_dst_cfg_0 = 0x0444;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_dst_cfg_1 = 0x0448;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_dst_cfg_2 = 0x044c;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_dst_cfg_3 = 0x0450;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_cmd_cfg_1 = 0x0454;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_start_cfg = 0x0458;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_read_status = 0x045c;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_read_sub_status_0 = 0x0460;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_read_sub_status_1 = 0x0464;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_read_sub_status_2 = 0x0468;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_read_sub_status_3 = 0x046c;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_rd_rslt_0 = 0x0470;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_rd_rslt_1 = 0x0474;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_rd_rslt_2 = 0x0478;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_rd_rslt_3 = 0x047c;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_rd_rslt_4 = 0x0480;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_rd_rslt_5 = 0x0484;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_rd_rslt_6 = 0x0488;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_rd_rslt_7 = 0x048c;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_write_status = 0x0490;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_write_sub_status_0 = 0x0494;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_write_sub_status_1 = 0x0498;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_write_sub_status_2 = 0x049c;
|
||||
inline constexpr uint32_t csr_offset_reg_csr_acc_write_sub_status_3 = 0x04a0;
|
||||
inline constexpr uint32_t csr_offset_reg_send_data_dma_cfg_0 = 0x0800;
|
||||
inline constexpr uint32_t csr_offset_reg_send_data_dma_cfg_1 = 0x0804;
|
||||
inline constexpr uint32_t csr_offset_reg_send_data_dma_cfg_2 = 0x0808;
|
||||
inline constexpr uint32_t csr_offset_reg_send_data_lock_cfg_0 = 0x080c;
|
||||
inline constexpr uint32_t csr_offset_reg_send_data_lock_cfg_1 = 0x0810;
|
||||
inline constexpr uint32_t csr_offset_reg_send_data_broadcast_cfg_0 = 0x0814;
|
||||
inline constexpr uint32_t csr_offset_reg_send_data_broadcast_cfg_1 = 0x0818;
|
||||
inline constexpr uint32_t csr_offset_reg_send_data_broadcast_cfg_2 = 0x081c;
|
||||
inline constexpr uint32_t csr_offset_reg_send_data_start_cfg = 0x0820;
|
||||
inline constexpr uint32_t csr_offset_reg_send_data_trans_status = 0x0824;
|
||||
inline constexpr uint32_t csr_offset_reg_send_data_trans_cmp_status_0 = 0x0828;
|
||||
inline constexpr uint32_t csr_offset_reg_send_data_trans_cmp_status_1 = 0x082c;
|
||||
inline constexpr uint32_t csr_offset_reg_send_data_trans_cmp_status_2 = 0x0830;
|
||||
inline constexpr uint32_t csr_offset_reg_send_data_trans_cmp_status_3 = 0x0834;
|
||||
inline constexpr uint32_t csr_offset_reg_send_data_ecc_status_0 = 0x0838;
|
||||
inline constexpr uint32_t csr_offset_reg_send_data_ecc_status_1 = 0x083c;
|
||||
} // namespace d2d_bridge_csr
|
||||
Reference in New Issue
Block a user